Method for Manufacturing Semiconductor Device

ABSTRACT

The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN). Accordingly, the man-hours can be reduced and the manufacturing cost of the semiconductor device can be reduced.

BACKGROUND OF THE INVENTION

The present invention relates to a method for manufacturing asemiconductor device, and more particularly to a technique which can beeffectively used for the manufacturing of high frequency power amplifierwhich is mainly comprised of hetero junction bipolar transistors (HBT)which constitute ultrahigh-speed IC elements.

As a semiconductor device which exhibits high speed performance and lowpower consumption performance, a hetero junction bipolar transistor(hereinafter also referred to as HBT) has been known. This heterojunction bipolar transistor is used in a form that the transistor isincorporated into a high frequency power amplifier (RF power amplifyingmodule) of a mobile communication terminal such as a portable cellularphone.

The HBT has a structure in which a sub-collector layer and a collectorlayer are sequentially laminated onto one surface (main surface) of asemiconductor substrate, a base layer is partially formed over thecollector layer, and an emitter layer which is formed of a semiconductorhaving a wide band gap is partially formed over the base layer.

In a power amplifying device for transmission in a communication system,the HBT has now been used as a transistor. Such a semiconductor deviceis described in Japanese Laid-open Patent 210723/2001.

In Japanese Laid-open Patent 210723/2001, a technique for manufacturinga semiconductor device having a bias circuit which suppresses a changeof an idle current attributed to a temperature change of a powertransistor Tr1 is disclosed. Such a semiconductor device is manufacturedusing a GaAs substrate as a base and, for compensating for a temperatureshift of the idle current, a plurality of Schottky diodes are providedto a base inputting part. The bias circuit is constituted of twotransistors (Tr2, Tr3) which are connected to the power transistor Tr1,two Schottky diodes (D1, D2) and three resisters (R1 to R3).

That is, a base terminal of the power transistor Tr1 is connected to acollector terminal of the transistor Tr2 through a resistor R3 in anemitter follower method, and a base terminal of the transistor Tr2 isgrounded through the transistor Tr3 which short-circuits a base and acollector of the Schottky diodes D1, D2 thus suppressing the change ofthe idle current C of the transistor Tr1 which is generated when thetemperature changes.

Further, with respect to this semiconductor device, base electrodes andthe Schottky electrodes of the HBT are simultaneously formed at the timeof manufacturing the semiconductor device.

On the other hand, in the manufacturing of the HBT, for preventing anexcessive etching of the sub-collector layer, there has been known atechnique which provides an InGaP layer between the sub-collector layerand the collector layer. This technique is described in IEEE ElectronDevice Lett., vol. 18, p355, 1997.

Further, in IEEE Electron Device Lett., vol. 18, p559, 1997, there isdisclosed a technique which enhances the isolation performance byarranging an undoped InGaP layer having a resistance higher than aresistance of an undoped GaAs layer below a collector layer.

SUMMARY OF THE INVENTION

As a transistor which constitutes a high frequency power amplifier (RFpower module) for a mobile communication unit, a hetero junction bipolartransistor (HBT) which constitutes a ultra high-speed IC element hasbeen used. Further, to compensate for a temperature shifting of an idlecurrent in the transistor, a bias circuit which provides a plurality ofSchottky diodes to a base inputting part is incorporated. Resistanceelements are also incorporated in this bias circuit.

The reduction of manufacturing cost has been requested with respect tothe HBT in the same manner as other transistors and modules. Withrespect to the power transistor into which the bias circuit isincorporated, as described in the above-mentioned literature, there hasbeen proposed the method which simultaneously forms the Schottkyelectrodes and the base electrodes using a same material.

To explain manufacturing steps thereof, as shown in FIG. 23(a), asemiconductor layer (n⁺ type GaAs layer) below an emitter electrode 56is etched using the emitter electrode 56 as a mask until the etchingreaches a surface of a semiconductor layer (n type InGaP layer) whichconstitutes a wide gap emitter layer 54 below the semiconductor layer(n⁺ type GaAs layer) thus forming a mesa-shaped emitter layer 55.

Thereafter, an etching mask not shown in the drawing is formed and, asshown in FIG. 23(a), using this etching mask as a mask, a semiconductorlayer which constitutes the wide gap emitter layer 54 which is exposedin a periphery of the emitter layer 55, a semiconductor layer (p-typeGaAs layer) which constitutes a base layer 53 below the semiconductorlayer, and a semiconductor layer (n⁺ type GaAs layer) 52 a whichconstitutes a collector layer below the base layer 53 are sequentiallyetched, wherein the semiconductor layer 52 a is etched to anintermediate depth thereof, thus forming the base layer having a mesashape (mesa-shaped base layer) 53.

Subsequently, a base electrode 57 and a Schottky electrode 58 aresimultaneously formed, wherein the base electrode 57 is formed over thewide gap emitter layer 54 in the periphery of the emitter layer 55 andthe Schottky electrode 58 is formed over the semiconductor layer (n⁺type GaAs layer) 52 a which constitutes a collector layer in a Schottkydiode forming region which is disposed away from a region where the HBTis formed. The base electrode 57 is subjected to an alloying treatment(heating treatment).

As a result, the wide gap emitter layer 54 below the base electrode 57is alloyed so that a base electrode 57 and the base layer 53 areelectrically connected to each other.

Further, in the manufacturing of the HBT, as shown in FIG. 23(a), asubstrate (wafer) which is eventually produced by sequentially formingrespective semiconductor layers consisting of a sub collector layer 51,the collector layer 52, the mesa-shaped base layer 53, the wide gapemitter layer 54 and the emitter 55 over one surface (main surface) of asemi-insulation GaAs substrate 50 is used.

However, in the method which forms the base electrode over thesemiconductor layer which constitutes the wide gap emitter layer 54, itis necessary to form holes for forming the base electrode in the etchingmask. Accordingly, in view of the mask alignment tolerance for formingthis hole, it is necessary to ensure the mask alignment tolerance lengthbetween an outer periphery of the base electrode 57 and an outerperiphery of a mesa-shaped base layer 53 in FIG. 23(b). As a result, ajunction area between the base layer 53 and the collector layer 52 isincreased. The increase of the area between the base and the collectordeteriorates the high frequency characteristics (for example, maximumoscillation frequency f max).

Then, as shown in FIG. 24, when the mask alignment tolerance length isshortened, the outer periphery of the base electrode 57 extends beyondthe periphery of the mesa-shaped base layer 53 and is brought intocontact with the collector layer 52 (contact portion 70) thus givingrise to a short-circuit defect. This leads to the lowering of a yieldfactor and brings about a drawback that a manufacturing cost is pushedup.

To prevent the outer periphery of the base electrode 57 from extendingbeyond the mesa-shaped base layer 53 and coming into contact with thesemiconductor layer (n⁺ type GaAs layer) 52 a which constitutes thecollector layer, it is necessary to ensure a minimum mask alignmenttolerance length “a”. FIG. 25 is a schematic view for showing the sizerelationship among respective portions in the manufacturing of the HBTwhile ensuring the mask alignment tolerance length “a”.

A base-collector junction length L2 is a length which is obtained byadding 2× mask alignment tolerance length “a” to a distance (distancebetween outer peripheries) “b” between one outer periphery of the baseelectrode 57 and another outer periphery which is disposed opposite toone outer periphery of the base electrode 57 and hence, the highfrequency power amplifier becomes large-sized. The distance betweenouter peripheries (“b”) is a sum of a width “d” of the base electrode57, a length “c” of the emitter electrode 56 and a distance “e” from aperiphery of the emitter electrode 56 to an inner periphery of the baseelectrode 57.

The inventors of the present invention have studied the above-mentioneddistances and widths from a viewpoint of miniaturization of the HBTelement and have obtained following sizes of respective portions as aresult of the study. That is, the lengths and the widths are set suchthat c=4 μm, d=1 μm, e=1 μm and b=8 μm. Further, by setting the maskalignment tolerance length “a” as a=0.8 μm, the base-collector junctionlength L2 becomes 9.6 μm.

On the other hand, to ensure the insulation separation (isolation)between the HBT and the other element arranged close to the HBT, therehas been known a structure which provides a separation groove betweenthe elements by etching. In performing this etching, when the etching isinsufficient, the separation groove is not formed thus giving rise to ashort-circuit defect, while when the etching is excessive, a largestepped portion is formed and hence, a line which is arranged traversingthe stepped portion is disconnected due to the large stepped portion.

FIG. 26 is a schematic view showing an example of a defect caused by theinsufficient etching or the excessive etching. For example, an areainside a left frame in FIG. 26 constitutes a region A for forming theHBT and an area inside a right frame in FIG. 26 constitutes a region Bfor forming another element such as a Schottky diode, for example. Inthe region A for forming the HBT, lines “a” to “c” which arerespectively connected to an emitter electrode E, a base electrode B anda collector electrode C traverse the separation groove, while in theregion B for forming the Schottky diode, a line “d” which is connectedto a Schottky electrode st traverses the separation groove.

When the etching becomes insufficient in the formation of the separationgroove, there arises a case that a defective isolation is generatedbetween the region A for forming the HBT and the region B for formingthe Schottky diode as indicated by (1) in FIG. 26. Further, when theetching is excessive, a stepped portion of the separation groove at theperiphery of the region A for forming the HBT or the periphery of theregion B for forming the Schottky diode is enlarged and hence, the line“a”, the line “c” or the line “d” is disconnected at the stepped portionas indicated by (2) in FIG. 26. Further, when the stepped portion islarge, in forming the lines by etching, the etching of the portion whichis arranged along the stepped portion can not be performed favorably andhence, a metal layer for forming the line remains as indicated by (3) inFIG. 26. The lines which are arranged closed to each other are connecteddue to this residual metal h thus giving rise to a short-circuit defect.Such an excessive or insufficient etching lowers a manufacturing yieldfactor thus pushing up a product cost.

Accordingly, it is an object of the present invention to provide amethod for manufacturing a semiconductor device which can achieve theenhancement of a yield factor as well as the reduction of amanufacturing cost.

It is another object of the present invention to provide a method formanufacturing a semiconductor device which exhibits the excellent highfrequency characteristics and can be manufactured at a low cost bynarrowing an area between a base and collector in a hetero junctionbipolar transistor.

The above-mentioned and other objects and novel features of the presentinvention will become apparent from the description of thisspecification and attached drawings.

To briefly explain the summary of typical inventions described in theinventions disclosed in the present application, they are as follows.

(1) In a method for manufacturing a semiconductor device in which aplurality of semiconductor layers are sequentially formed in a laminatedmanner over a semiconductor substrate, a hetero junction bipolartransistor, a Schottky diode and a resistance element are formed in amonolithic manner, and a separation groove for establishing an electricinsulation is formed at least between the hetero junction bipolartransistor and the Schottky diode,

respective semiconductor layers which are formed into a sub collectorlayer, a collector layer, a base layer, a wide gap emitter layer and anemitter layer are sequentially formed over one surface of thesemiconductor substrate and, thereafter, in the manufacture of thehetero junction bipolar transistor, among the above-mentioned respectivesemiconductor layers, given semiconductor layers are formed in givenpatterns by sequential etching thus sequentially forming an emitterlayer, a wide gap emitter layer, a base layer, a collector layer and asub collector layer, and at the same time, an emitter electrode isformed over the emitter layer, an alloying treatment is applied to thewide gap emitter layer which extends around the emitter layer thusforming a base electrode which is electrically connected to the baselayer, and a collector electrode is formed over the collector layerwhich extends around the base layer thus forming the hetero junctionbipolar transistor,

in the manufacture of the Schottky diode, a Schottky electrode is formedover a semiconductor layer corresponding to the collector layer, and anohmic electrode for diode is formed over a semiconductor layercorresponding to the sub collector layer thus forming the Schottkydiode,

in the manufacture of the resistance element, a resistance film isformed over an insulation film in a region outside a region where thehetero junction bipolar transistor and the Schottky diode are formed,and the Schottky electrode and the resistance film are simultaneouslyformed using a same material.

Further, the semiconductor substrate is formed of a semi-insulating GaAssubstrate, the sub collector layer is formed of a first conductive-typeGaAs layer, the collector layer is formed of a first conductive-typeGaAs layer, the base layer is formed of a second conductive-type GaAslayer, the wide gap emitter layer is formed of a first conductive-typeInGaP layer, the emitter layer is formed of a first conductive type GaAslayer having an InGaAs layer as a surface layer thereof, the etchingstopper layer is formed of a first conductive-type InGaP layer. TheSchottky electrode and the resistance film are made of alloy whichmainly contains a high melting-point material or a silicide and havegiven portions on which lines made of aluminum are overlapped.

Due to such a constitution, the Schottky diode and the resistance filmcan be formed simultaneously and hence, man-hours can be reduced so thata product cost can be reduced.

(2) In the above-mentioned constitution (1), the base electrode isformed such that the base electrode surrounds the emitter layer and, atthe same time, a region ranging from the base electrode to the inside ofthe base electrode except for an outer periphery of the base electrodeis covered with a mask for etching, and the collector layer is etched toan intermediate depth thereof using the mask for etching and the baseelectrode as masks thus forming the mesa-shaped base layer. Due to sucha constitution, it is possible to reduce a base-collector junction areaso that the high frequency characteristics (for example, maximumoscillation frequency fmax and the like) of the hetero junction bipolartransistor can be enhanced.

(3) In the above-mentioned constitution (1), an etching stopper layerwhich is formed of a material having an etching speed lower than anetching speed of the sub collector layer is formed between thesemiconductor substrate and the sub collector layer and, at the sametime, an etching stopper layer which is formed of a material having anetching speed lower than an etching speed of the collector layer isformed between the sub collector layer and the collector layer,

an etching which is performed to expose the sub collector layer byetching the collector layer is completed by stopping the etching at theetching stopper layer, and

the formation of the separation groove includes an etching treatment inwhich etching of the sub collector layer is stopped at the etchingstopper layer, an etching treatment in which the etching stopper layeris etched, and an etching treatment in which a surface layer portion ofthe semiconductor substrate is etched. Due to such a constitution, it ispossible to prevent a shortage of etching and an excessive etching andso that an isolation defect attributed to the shortage of etching can besuppressed and a disconnection of lines or a short-circuit between lineswhich occurs at a stepped portion attributed to the excessive etchingcan be prevented whereby a manufacturing yield factor is enhanced and aproduction cost can be reduced. This constitution (3) is particularlyeffective (a) when it is necessary to lower the resistance of the subcollector by increasing a thickness of the sub collector layer and (b)when it is necessary to increase a collector breakdown strength and toreduce a collector capacitance by increasing a thickness of thecollector layer. For example, with respect to a GaAs HBT for power use,a sub collector layer and a collector layer whose total thickness isequal to or more than 1 μm are usually used.

BRIEF EXPLANATION OF THE DRAWINGS

FIG. 1 is a cross-sectional view showing a portion of a high frequencypower amplifier in which a bias circuit is incorporated according to oneembodiment (embodiment 1) of the present invention.

FIG. 2 is an equivalent circuit diagram of the high frequency poweramplifier of the embodiment 1.

FIG. 3 is a cross-sectional view of a portion of a semiconductorsubstrate on which a mesa-shaped emitter layer is formed in a method formanufacturing the high frequency power amplifier of the embodiment 1.

FIG. 4 is a cross-sectional view of a portion of a semiconductorsubstrate on which a base electrode is formed in a method formanufacturing the high frequency power amplifier of the embodiment 1.

FIG. 5 is a cross-sectional view of a portion of a semiconductorsubstrate on which a mesa-shaped base layer is formed in a method formanufacturing the high frequency power amplifier of the embodiment 1.

FIG. 6 is a cross-sectional view of a portion of a semiconductorsubstrate on which a collector electrode and a diode electrode areformed in a method for manufacturing the high frequency power amplifierof the embodiment 1.

FIG. 7 is a cross-sectional view of a portion of a semiconductorsubstrate which is subjected to a first etching treatment for forming aseparation groove in a method for manufacturing the high frequency poweramplifier of the embodiment 1.

FIG. 8 is a cross-sectional view of a portion of a semiconductorsubstrate which is subjected to a second etching treatment for forming aseparation groove in a method for manufacturing the high frequency poweramplifier of the embodiment 1.

FIG. 9 is a cross-sectional view of a portion of a semiconductorsubstrate on which a Schottky electrode for diode and a resistance filmare formed in a method for manufacturing the high frequency poweramplifier of the embodiment 1.

FIG. 10 is a cross-sectional view of a portion of a semiconductorsubstrate on which lines are formed in a method for manufacturing thehigh frequency power amplifier of the embodiment 1.

FIG. 11 is a schematic view showing a miniaturized base-collectorjunction portion in the high frequency power amplifier of the embodiment1.

FIG. 12 is a graph showing the correlation between a base-collectorjunction area and the power adding efficiency in the semiconductordevice of the embodiment 1.

FIG. 13 is a cross-sectional view of a portion of a semiconductorsubstrate on which an interlayer insulation film which covers acollector electrode, a diode electrode and the like is formed in amethod for manufacturing a high frequency power amplifier in which abias circuit which constitutes another embodiment (embodiment 2) of thepresent invention is incorporated.

FIG. 14 is a cross-sectional view of a portion of a semiconductorsubstrate on which an emitter electrode and a Schottky electrode fordiode are formed in a method for manufacturing the high frequency poweramplifier of the embodiment 2.

FIG. 15 is a cross-sectional view of a portion of a semiconductorsubstrate on which a second interlayer film and a resistant film areformed in a method for manufacturing a high frequency power amplifier ofthe embodiment 2.

FIG. 16 is a cross-sectional view of a portion of a semiconductorsubstrate on which lines and a final passivation film are formed in amethod for manufacturing a high frequency power amplifier of theembodiment 2.

FIG. 17 is a cross-sectional view of a portion of a semiconductorsubstrate on which a mesa-shaped emitter layer is formed in a method formanufacturing a high frequency power amplifier in which a bias circuitis incorporated which constitutes another embodiment (embodiment 3) ofthe present invention.

FIG. 18 is a cross-sectional view of a portion of a semiconductorsubstrate on which a mesa-shaped base layer is formed in a method formanufacturing a high frequency power amplifier of the embodiment 3.

FIG. 19 is a cross-sectional view of a portion of a semiconductorsubstrate on which a collector electrode and an electrode for diode areformed in a method for manufacturing a high frequency power amplifier ofthe embodiment 3.

FIG. 20 is a cross-sectional view of a portion of a semiconductorsubstrate on which an interlayer insulation film is formed in a methodfor manufacturing a high frequency power amplifier of the embodiment 3.

FIG. 21 is a cross-sectional view of a portion of a semiconductorsubstrate on which an emitter electrode, a .Schottky electrode for diodeand a resistance film are formed in a method for manufacturing a highfrequency power amplifier of the embodiment 3.

FIG. 22 is a cross-sectional view of a portion of a semiconductorsubstrate on which lines and a final passivation film are formed in amethod for manufacturing a high frequency power amplifier of theembodiment 3.

FIG. 23 is a cross-sectional view of a portion of a semiconductorsubstrate in a given manufacturing step of a high frequency poweramplifier which is manufactured prior to the present invention.

FIG. 24 is a cross-sectional view of a portion of a semiconductorsubstrate showing a defective example in a given manufacturing step of ahigh frequency power amplifier which is manufactured prior to thepresent invention.

FIG. 25 is a schematic view showing a base-collector junction portion ina high frequency power amplifier which is manufactured prior to thepresent invention.

FIG. 26 is a schematic view showing a defective example attributed to ashortage of etching or an excessive etching in the formation of aseparation groove by etching.

DESCRIPTION OF PREFERRED EMBODIMENT

Preferred embodiments of the present invention are explained in detailhereinafter in conjunction with attached drawings. In all drawings whichare served for explaining the embodiments of the present invention,parts having same functions are indicated by same numerals or symbolsand repeated explanation thereof is omitted.

(Embodiment 1)

FIG. 1 to FIG. 12 are views which are related to a high frequency poweramplifier in which a bias circuit is incorporated and a method formanufacturing the high frequency power amplifier in one embodiment(embodiment 1) of the present invention. In these drawings, FIG. 1 is across-sectional view showing a portion of the high frequency poweramplifier and FIG. 2 is an equivalent circuit diagram of the highfrequency power amplifier, and FIG. 3 to FIG. 9 are cross-sectionalviews showing a portion of a semiconductor substrate in respectivemanufacturing steps of the high frequency power amplifier.

The semiconductor device 1 of the embodiment 1 is, as shown in FIG. 1,comprised of a hetero junction bipolar transistor (HBT) 20, a Schottkydiode 40 and a resistance element 45. These HBT 20, the Schottky diode40 and the resistance element 45 are formed by processing semiconductorlayers or the like which are formed in multi-layers on one surface (mainsurface) of a semiconductor substrate 2.

As the semiconductor substrate 2, a semi-insulating GaAs substrate 2 isused, for example. At a portion of the hetero junction bipolartransistor 20, on a portion of main surface of the above-mentionedsemi-insulating GaAs layer 2, a first conductive-type (n-type, forexample) n-type GaAs layer 4 is formed by way of an n-type InGaP layer3. The n-type InGaP layer 3 constitutes a sub collector layer 4 a andthis n-type InGaP layer 3 functions as an etching stopper layer when thesub collector layer 4 a is formed by etching the n-type GaAs layer 4.

Over the n-type GaAs layer 4, the n-type GaAs layer 6 is formed by wayof an n-type InGaP. layer 5. The n-type GaAs layer 6 constitutes acollector layer 6 a and the n-type InGaP layer 5 functions as an etchingstopper layer when the collector layer 6 a is formed by etching then-type GaAs layer 6.

Over the collector layer 6 a, a base layer 7 a which is constituted of asecond conductive p-type GaAs layer 7 is formed. The base layer 7 a isformed in a square shape and a base electrode 10 is formed over aperiphery thereof. Over the base layer 7 a inside the base electrode 10,a wide gap emitter layer 8 a which is constituted of an n-type InGaPlayer 8 is formed. The n-type InGaP layer 8 adopts the wide band gapconstitution.

Since the base layer 7 a is formed by etching which uses the baseelectrode 10 also as a mask for etching, the base layer 7 a is formedinto a mesa-shaped base layer in which the periphery of the base layer 7a is retracted inwardly from an outer periphery of the base electrode10. Accordingly, the outer periphery of the base electrode 10 projectsoutwardly from the base layer 7 a in an overhanging manner or likeeaves. The etching naturally reaches a surface layer portion of thecollector layer 6 a.

Further, since the base electrode 10 is subjected to the alloyingtreatment after the base electrode 10 is formed over the n-type InGaPlayer 8, the n-type InGaP layer 8 below the base electrode 10 is alloyedand the base electrode 10 is electrically connected to the base layer 7a through this alloy layer.

Over a portion of, that is, over a center portion of the wide gapemitter layer 8 a, an emitter layer 9 a which is constituted of ann-type InGaAs/n-type GaAs layer 9 (n-type GaAs layer having an n-typeInGaAs layer on a surface thereof for having an ohmic contact with anemitter electrode) is formed. An emitter electrode 11 is formed over theemitter layer 9 a. Since the emitter layer 9 a is formed by etchingusing the emitter electrode 11 which is formed over the n-typeInGaAs/n-type GaAs layer 9 (hereinafter simply expressed as the n-typeGaAs layer 9) as a mask for etching, an outer periphery of the emitterelectrode 11 also projects from a periphery of the emitter layer 9 a inan overhanging manner.

The collector layer 6 a which projects from the periphery of the baselayer 7 a and is disposed below the base layer 7 a by one stage has aportion thereof removed and a collector electrode 12 is formed over then-type InGaP layer 5 which is exposed by such a removal. Although then-type InGaP layer 5 which functions as an etching stopper layer isinterposed between the collector electrode 12 and the sub collectorlayer 4 a, since the layer is of n-type, the collector electrode 12 andthe sub collector layer 4 a are electrically connected to each other.

The HBT 20 is held in an electrically independent state by beingisolated. That is, a separation groove 13 which reaches a surface layerof the semi-insulating GaAs substrate 2 is formed in the periphery ofthe HBT 20 so that the HBT 20 has the electrically independentconstitution. Due to the formation of the separation groove 13 forisolation, the n-type GaAs layer 4 is formed into the sub collectorlayer 4 a in a region where the HBT 20 is formed.

The sub collector layer 4 a, the n-type InGaP layer 5, the collectorlayer 6 a, the base layer 7 a, the base electrode 10, the wide gapemitter layer 8 a, the emitter layer 9 a and the emitter electrode 11formed over the semi-insulating GaAs substrate 2 are covered with aninsulation film 14. Further, an interlayer insulation film 15 is formedover the insulation film 14 in an overlapped manner.

Contact holes are formed in the insulation film 14 and the interlayerinsulation film 15 at given places. Lines 16 having a given pattern areformed over these contact holes and the interlayer insulation film 15.Given portions of the lines 16 are respectively connected to the baseelectrode 10, the emitter electrode 11 and the collector electrode 12.The lines 16 are, for example, formed of aluminum.

Further, the lines 16 and the interlayer insulation film 15 are coveredwith an insulation film 17 which constitutes a final passivation film.Although not shown in the drawings, the insulation film 17 is partiallyremoved by etching so as to expose portions of lines-which constituteexternal electrode terminals. These external electrode terminalscorrespond to V1, Vcc2, Vcc in a circuit diagram shown in FIG. 2, forexample.

The Schottky diode 40 includes an n-type InGaP layer 3, an n-type GaAslayer 4, an n-type InGaP layer 5 and an n-type GaAs layer 6 which areformed in an overlapped manner over the semi-insulating GaAs substrate 2which is surrounded by the separation groove 13. A Schottky electrode 41which constitutes one electrode of the Schottky diode 40 is selectivelyformed over the n-type GaAs layer 6. Further, the n-type GaAs layer 6 ispartially removed by etching and an ohmic electrode 42 for diode whichconstitutes another electrode of the Schottky diode is formed over theexposed n-type InGaP layer 5.

The Schottky diode forming region which is surrounded by the separationgroove 13 is also covered with the insulation film 14 and the interlayerinsulation film 15 which is overlapped to the insulation film 14.Further, contact holes are formed at given places by selectivelyremoving the interlayer insulation film 15 and the insulation film 14.Lines 16 having a given pattern are formed over these contact holes andthe interlayer insulation film 15. Given portions of these lines 16 arerespectively connected to the Schottky electrode 41 and the ohmicelectrode 42 for diode. The lines 16 are formed of aluminum as mentionedabove.

The resistance element 45 is constituted of a resistance film 46 whichis selectively formed over the insulation film 14 which covers a surfaceof the semi-insulating GaAs substrate 2 which is etched at the time offorming the separation groove 13 and lines 16 which are connected torespective ends of the resistance film 46. That is, the resistance film46 is covered with the interlayer insulation film 15, contact holes areformed in the interlayer insulation film 15 at portions thereofcorresponding to both end portions of the resistance film 46, and thelines 16 are electrically connected to the resistance film 46 throughthe contact holes.

In this embodiment 1, the Schottky electrode 41 and the resistance film46 are formed simultaneously using the same material. Further, to formthe resistance film and to establish the Schottky junction, the Schottkyelectrode 41 and the resistance film 46 are formed of alloy containingmainly a high melting point material such as WSIN or silicide. A filmthickness of the WsiN film is, for example, 0.1 to 0.5 μm and is 0.2 μmin this embodiment 1.

To reduce the electric resistance of the Schottky electrode 41, the filmthickness of the WSiN film is set thin, that is, to 0.2 μm and, at thesame time, the line 16 which is connected to the WSiN film is overlappedto the WSiN film by a given length. Here, the lines 16 may be formed ofa metal layer for reducing the electric resistance.

When the size of the Schottky electrode 41 is set to the size of 10μm×10 μm, the parasitic resistance is 0.2 Ω even when the thickness ofthe WSiN is 1 μm and hence, there arises no problem. Further, withrespect to the resistance film, the film is made thin to maintain theflatness. The resistance ratio ρ of WSiN is changed corresponding to thecomposition of nitrogen and silicon and can take a resistance value of500 to 5000 μΩcm, for example. In this case, the sheet resistance ρs ofthe resistance film can be set to 10 to 500 Ω/□ based on a formulaρs=ρ/t, wherein t is a thickness of the resistance film.

Further, as the material of Schottky electrode and the resistance film,WSi, WN, TaSi, TaN, TaSiN, TiN, TiSiN, MoSi, MoSiN and the like can beused.

In this embodiment 1, the emitter electrode 11 is formed of WSi, thebase electrode 10 is formed of Au/Ti/Mo/Ti/Pt, and the collectorelectrode 12 and the ohmic electrode 42 for diode are formed of AuGe.

Then, the method for manufacturing the semiconductor device 1 isexplained in conjunction with FIG. 3 to FIG. 10.

By sequentially laminating the n-type InGaP layer 3, the n-type GaAslayer 4, the n-type InGaP layer 5, the n-type GaAs layer 6, the p-typeGaAs layer 7, the n-type InGaP layer 8, and the n-type GaAs layer 9 to amain surface of the semi-insulating GaAs substrate 2 using a MOCVD(Metalorganic Chemical Vapor Deposition) method or the like, a wafer 25is formed. The n-type InGaP layer 8 constitutes the wide band gap layer.To show an example of thicknesses of respective semiconductor layers,the semi-insulating GaAs substrate 2 has a thickness of 625 μm, then-type InGaP layer 3 has a thickness of 20 nm, the n-type GaAs layer 4has a thickness of 700 nm, the n-type InGaP layer 5 has a thickness of20 nm, the n-type GaAs layer 6 has a thickness of 700 nm, the p-typeGaAs layer 7 has a thickness of 100 nm, the n-type InGaP layer 8 has athickness of 35 nm, and the n-type InGaAs/ n-type GaAs layer 9 (then-type GaAs layer 9) has a thickness of 400 nm. The n-type InGaAs layerwhich constitutes a surface layer of the n-type InGaAs/n-type GaAs layer9 is a layer having an ohmic contact with an emitter electrode and. hasa thickness of approximately 100 nm. Here, since the n-type InGaP layer3 is necessary in a method for separating elements, in many cases, thelayer 3 may be preferably formed of an n-type layer having lowconcentration by suppressing n-type impurities. Further, although theGaAs substrate 2 has a thickness of 625 μm at the time of manufacturingthe substrate 2 initially, the thickness is reduced to 100 to 50 μm atthe final manufacturing step and hence, the thermal resistance of thesemiconductor substrate is lowered so that the GaAs substrate 2 can beused as a product.

Subsequently, as shown in FIG. 3, the emitter electrode 11 having agiven size is formed over the n-type GaAs layer 9 using aphotolithography technique and an etching technique which are adoptedusually. The emitter electrode 11 is formed of WSi, for example, and isformed with a thickness of approximately 200 nm. Thereafter, the n-typeInGaAs/n-type GaAs layer 9 is etched using the emitter electrode 11 asan etching mask. The etching is performed by wet etching which uses amixed aqueous solution of phosphoric acid and hydrogen peroxide. Sincethe n-type InGaP layer 8 functions as an etching stopper layer, it ispossible to surely remove the n-type InGaAs/n-type GaAs layer 9 byselecting an etching time. Due to this wet etching, the mesa-shapedemitter layer 9 a can be formed.

Subsequently, as shown in FIG. 4, the base electrode 10 is formed usinga lift-off method and an alloying treatment. That is, an insulation filmmade of SiO₂ is formed over a whole area of a surface of the wafer 25,openings are formed in the insulation film at some places using a photoresist, and a metal film is formed over the insulation film by asputtering method. For example, a multi-layered film (thickness: 300 nm)formed of Au/Ti/Mo/Ti/Pt which uses Pt as a lowermost layer is formed bya sputtering method. Thereafter, electrodes can be formed in the openingportions by removing the photo resist. Then, the alloying treatment isperformed by heat treatment. Due to this alloying treatment, Pt whichconstitutes the lowermost layer is alloyed by the reaction with then-type InGaP layer 8 and the p-type GaAs layer 7 and is brought into anohmic contact with the p-type GaAs layer 7. The base electrode 10 is, asshown in FIG. 1, formed such that the base electrode 10 surrounds theemitter layer 9 a.

Subsequently, as shown in FIG. 5, to form the mesa-shaped base layer, aphoto resist film 26 is selectively formed over a surface of the wafer25. The photo resist film 26 is formed such that the photo resist film26 extends over the base electrode 10 which is arranged to surround theemitter layer 9 a from above the emitter layer 9 a. To use the baseelectrode 10 as an etching mask, the photo resist film 26 is formed suchthat an outer periphery of the base electrode 10 is exposed. Then, usingthe base electrode 10 and the photo resist film 26 as masks, the n-typeInGaP layer 8 and the p-type GaAs layer 7 which is disposed below then-type InGaP layer 8 are etched. In etching the p-type GaAs layer 7, asurface layer portion of the n-type GaAs layer 6 is also etched. Withthis etching, the mesa-shaped base layer 7 a is formed. Here, an upperperiphery of the base layer 7 a is disposed at a position inside theouter periphery of the base electrode 10 by “g”.

The etching of the n-type InGaP layer 8 is performed by wet etchingwhich uses hydrochloric acid and the etching of the p-type GaAs layer 7and the surface layer portion of the n-type GaAs layer 6 is performed bywet etching which uses a mixed aqueous solution of phosphoric acid andhydrogen peroxide. Since the n-type GaAs layer 6 is etched byapproximately 300 nm, the n-type GaAs layer 6 still maintains athickness of approximately 400 nm. After performing etching, the photoresist film 26 is removed.

Depending on the degree of this etching, the size (area and length) ofthe base-collector junction is determined. FIG. 11 is a schematic viewshowing the base-collector junction portion. The drawing corresponds toFIG. 25 and shows a state in which the miniaturization of thebase-collector junction is achieved due to the embodiment 1.

According to this embodiment 1, the etching is performed by making useof the base electrode 10 as the etching mask and hence, a base-collectorjunction length L1 becomes shorter than a distance between one outerperiphery of the base electrode 10 and the other outer periphery opposedto the one outer periphery (distance between outer peripheries) “b” dueto an action of side etching and becomes shorter than a base-collectorjunction length L2 shown in FIG. 25. In FIG. 11, the base-collectorjunction length L2 is indicated for a comparison purpose. The distancebetween outer peripheries “b” is a sum of a width “d” of the baseelectrode 10, a length “c” of the emitter electrode 56 and a distance“e” from a periphery of the emitter electrode 56 to an inner peripheryof the base electrode 10.

According to this embodiment 1, when the distance between outerperipheries “b” of the base electrode 10 is set to 8 μm in the samemanner as the structure shown in FIG. 25, the outer peripheries of themesa-shaped base layer 7 a are respectively retracted toward the insideby 0.4 μm by side etching and hence, the base-collector junction lengthL1 takes a small value, that is, 7.2 μm. This value is smaller by 2.4 μmthan the value shown in FIG. 25. Accordingly, it is possible tominiaturize the hetero junction bipolar transistor 20.

Subsequently, as shown in FIG. 6, an insulation film 27 having athickness of 100 nm which is made of SiO₂ is formed over the surface ofthe wafer 25. Thereafter, the n-type GaAs layer 6 is selectively etchedby the photolithography technique or the etching technique which areusually employed so as to form contact holes for forming electrodes.Then, the collector electrode 12 and the ohmic electrode 42 for diodeare formed by a lift-off method. The collector electrode 12 and theohmic electrode 42 for diode having a thickness of 300 nm are formedusing AuGe by a sputtering method.

In etching the above-mentioned n-type GaAs layer 6, wet etching whichuses a mixed aqueous solution of phosphoric acid and hydrogen peroxideis adopted and hence, although it is possible to completely etch then-type GaAs layer 6 in the etching region, the n-type InGaP layer 5below the n-type GaAs layer 6 is not etched. Accordingly, the thicknessof the n-type GaAs layer 4 is not changed so that the collectorresistance value is not changed whereby there is no possibility that thecollector resistance is increased by etching.

Subsequently, the insulation film 28 for forming the separation groovefor isolation is selectively formed over the surface of the wafer 25 bythe photolithography technique and the etching technique which areusually employed. The insulation film 28 is made of SiO₂ and theinsulation film 27 is integrally formed with the insulation film 28.Accordingly, the symbol is set to 28.

As shown in FIG. 7, using the insulation film 28 as a mask, the n-typeGaAs layer 6 is etched using a mixed aqueous solution of phosphoric acidand hydrogen peroxide. Subsequently, the n-type InGaP layer 5 is etchedby etching which uses hydrochloric acid as an etchant. Then, the n-typeGaAs layer 4 is etched by etching which uses a mixed aqueous solution ofphosphoric acid and hydrogen peroxide as an etchant. In this state, then-type InGaP layer 3 remains as shown in FIG. 7.

Subsequently, as shown in FIG. 8, using the insulation film 28 as amask, the n-type InGaP layer 3 is successively etched by etching whichuses hydrochloric acid as an etchant. Subsequently, a surface layer ofthe semi-insulating GaAs substrate 2 is etched to a given depth byetching which uses a mixed aqueous solution of phosphoric acid andhydrogen peroxide as an etchant. Accordingly, the separation groove 13is formed around regions on which the HBT and the Schottky diode areformed. In the resistance element forming region, a surface layerportion of the semi-insulating GaAs substrate 2 is etched. Although aportion of the semi-insulating GaAs substrate 2 is also etched in thisembodiment, etching may be stopped in a state that the n-type InGaPlayer 3 is etched.

In the formation of this separation groove 13, to perform etching of then-type GaAs layer 4, after stopping the etching at the n-type InGaPlayer 3 which constitutes an etching stopper layer, the n-type InGaPlayer 3 is etched and, thereafter, a surface layer portion of thesemi-insulating GaAs substrate 2 which exposes a surface thereof isetched to a given depth (50 μm, for example). By adopting such atechnique, it is possible to always set a height of the groove bottom ofthe separation groove 13 to a fixed value. This is because that a depthof etching of the surface layer portion of the semi-insulating GaAssubstrate 2 is short and hence, the depth of etching can be accuratelycontrolled based on the etching time.

That is, respective semiconductor layers have irregularities inthickness when they are formed and hence, in the formation of theseparation groove 13 by etching, when either one of a method (1) inwhich the n-type GaAs layer 6, the n-type GaAs layer 4 and thesemi-insulating GaAs substrate 2 are etched under time control withoutforming an etching stopper layer in an intermediate portion thereof anda method (2) in which the n-type GaAs layer 4 and the semi-insulatingGaAs substrate 2 are etched under time control without forming anetching stopper layer in an intermediate portion thereof, the depth ofetching becomes deep. Accordingly, the etching time is prolonged and theirregularities of the depth of the separation groove 13 is increased sothat the shortage of etching or the excessive etching is liable toeasily occur.

To the contrary, the height of the groove bottom of the separationgroove 13 in the first embodiment 1 is determined based on the etchingfrom the surface of the semi-insulating GaAs substrate 2 which isexposed by removing the n-type InGaP layer 3 and the depth of etching isalso shallow, that is approximately 50 μm, for example. Accordingly,even when the etching under time control is performed, theirregularities in the depth of the groove bottom becomes small so that astep of the separation groove 13 portion takes a proper value and hence,a large step is not formed.

Due to the formation of the separation groove by etching which adoptssuch an etching treatment technique, the shortage of etching and theexcessive etching can be prevented. As a result, it is possible toprevent the occurrence of the isolation failure between the region wherethe HBT is formed and the region where the Schottky diode is formed asindicated by (1) shown in FIG. 26. It is also possible to prevent thedisconnection of lines at the stepped portion indicated by (2) in FIG.26. Further, it is possible to prevent the occurrence of short-circuitfailure between the lines which is attributed to the residue of themetal layer at a portion along the step indicated by (3) in FIG. 26.

Subsequently, as shown in FIG. 9, the insulation film 14 having athickness of 400 nm and made of SiO₂ is formed over a whole area of thesurface of the wafer 25 and, thereafter, an opening is selectivelyformed in the insulation film 14 over the n-type GaAs layer 6 in theSchottky diode forming region. Then, the Schottky electrode 41 is formedin the above-mentioned opening portion and, at the same time, theresistance film 46 is formed over the insulation film 14 in theresistance element forming region. The Schottky electrode 41 and theresistance film 46 are simultaneously formed using the same material.That is, for example, the WSiN film having a thickness of 200 nm isformed by a sputtering method and, thereafter, the patterning isperformed as shown in FIG. 9 by dry etching using a SF6 gas or the like.The sheet resistance value of the WSiN film having a thickness of 200 nmis 50 to 100 Ω. Although the film thickness of the WSiN film may be setto a value which falls in a range of approximately 0.1 to 0.5 μm, forexample, the film thickness is set to 0.2 μm in this embodiment 1.

To form the resistance film and to establish the Schottky junction, theSchottky electrode 41 and the resistance film 46 are formed of alloywhich is mainly made of a high melting-point material such as WSiN orthe like or silicide. As the material of the Schottky electrode and theresistance film, WSi, WN, TaSi, TaN, TaSiN, TiN, TiSiN, MoSi, MoSiN andthe like can be used. The silicide which constitutes high melting-pointmetal forms the Schottky electrode which is stable against GaAs.

Subsequently, as shown in FIG. 10, the interlayer insulation film 15having a thickness of 500 nm and made of SiO₂ is formed over the entirearea of the surface of the wafer 25 and, thereafter, contact holes areselectively formed and the lines 16 are selectively formed using aphotolithography technique and an etching technique which are usuallyadopted. As shown in FIG. 10, the contact holes are formed such that thecontact holes face the emitter electrode 11, the base electrode 10, thecollector electrode 12, the ohmic electrode 42 for diode, the Schottkyelectrode 41 and two portions of the resistance film 46. The lines 16which are filled in these contact holes are electrically connected torespective electrodes (resistance films).

To reduce the electric resistance of the Schottky electrode 41, the filmthickness of the WSiN film is made small, that is, 0.2 μm and, at thesame time, the line 16 which is connected to the WSiN film is overlappedto the WSIN film by a given length. Here, a gold layer may be used asthe line 16 to reduce the electric resistance.

Provided that the size of the Schottky electrode 41 is set to a size of10 μm×10 μm, even when the thickness of the WSiN film is 1 μm, theparasitic resistance is 0.2 Ω and hence, there is no problem. Further,with respect to the resistance film, the film is made thin to maintainthe flatness. The resistance ratio ρ of WSiN is changed corresponding tothe composition of nitrogen and silicon and can take a resistance valueof 500 to 5000 μΩcm, for example. In this case, the sheet resistance ρsof the resistance film can be set to 10 to 500 Ω/□ based on a formulaρs=ρ/t, wherein t is a thickness of the resistance film.

Although not shown in the drawing, another second lines may be formedapart from the lines 16 when necessary.

Subsequently, the insulation film 17 having a total thickness of 600 nmwhich is formed of the SiN film and the SiO₂ film (see FIG. 1) is formedover the whole area of the surface of the wafer 25 as a passivationfilm. Then, the thickness of the semi-insulating GaAs substrate 2 isreduced to 100 to 50 μm as described previously, and the semi-insulatingGaAs substrate 2 is divided by cutting longitudinally as well aslaterally so as to produce the semiconductor devices 1. A portion of thesemiconductor device 1 is shown in FIG. 1.

By adopting such a method for manufacturing the HBT, the diode and theresistance, the semiconductor device 1 has the constitution which isexpressed as an equivalent circuit shown in FIG. 2. That is, theequivalent circuit is comprised of a power transistor Tr3 and a biascircuit which suppresses the change of an idle current attributed to thetemperature change of the power transistor Tr3. A collector electrode ofthe power transistor Tr3 is connected to a power supply voltage Vcc andan emitter electrode of the power transistor Tr3 is earthed (grounded).A base electrode of the power transistor Tr3 is connected to an emitterelectrode of a transistor Tr2 through a resistance element R4 and a biaspotential is given by a resistance element R5.

A collector electrode of the transistor Tr2 is connected to a powersupply voltage Vcc 2 and an emitter electrode of the transistor Tr2 isgrounded through the resistance element R5. A base electrode of thetransistor Tr2 is connected to a power supply voltage V1 through aresistance element R1 and, at the same time, a bias voltage is given tothe bias electrode through the Schottky diodes S1, S2, a transistor Tr1which has a base and a collector thereof short-circuited and aresistance element R2. Due to such a constitution, the change of theidle current which is generated when temperature changes and flows intothe transistor Tr3 can be suppressed.

Following advantageous effects can be obtained by the first embodiment.

(1) Since the Schottky electrode 41 of the Schottky diode and theresistance film 46 of the resistance element are simultaneously formedusing the same material (WSiN), the number of steps can be reduced sothat the manufacturing cost of the semiconductor device can be reduced.

(2) The base electrode 10 is formed such that the base electrode 10surrounds the emitter electrode 11, the mask for etching is formed tothe portion including the base electrode 10 and the emitter electrode 11except for the outer periphery of the base electrode 10, and themesa-shaped base layer 7 a is formed using this mask and the emitterelectrode 11 as masks and hence, the base-collector junction area can bereduced by side etching whereby the capacitance between the base and thecollector can be reduced. Accordingly, the basic high frequencycharacteristics (for example, maximum oscillation frequency f max andthe like) of the hetero junction bipolar transistor can be enhanced sothat the high-speed operation and high performance of the heterojunction bipolar transistor can be further enhanced. FIG. 12 is a graphshowing the correlation between the base-collector junction area and thepower adding efficiency. As can be understood from this graph, when thesum of the base-collector junction areas of the HBT in all power stagesis reduced by 20%, the power adding efficiency is enhanced byapproximately 2%. This is an example of evaluation of GaAs-HBT forportable cellular phone.

(3) In performing etching of the n-type GaAs layer 6, the wet etchingwhich uses the mixed aqueous solution of phosphoric acid and hydrogenperoxide is adopted and hence, although the n-type GaAs layer 6 can beetched completely in the etching region, the n-type InGaP layer 5disposed below the n-type GaAs layer 6 is not etched. Accordingly, sincethe thickness of the n-type GaAs layer 4 is not changed and hence, theresistance value of the collector is not changed so that there is nopossibility that the collector resistance is increased whereby it ispossible to manufacture the hetero junction bipolar transistors whichexhibit the stable characteristics.

(4) This embodiment adopts the structure in which the n-type InGaP layer3 which constitutes the etching stopper layer is formed over the mainsurface of the semi-insulating GaAs substrate 2 and the n-type GaAslayer 4 is formed over the n-type InGaP layer 3. Accordingly, in formingthe groove bottom of the separation groove 13, the etching of the n-typeGaAs layer 4 is stopped at the n-type InGaP layer 3 and, thereafter, then-type InGaP layer 3 is etched by etching which uses a differentetchant. Here, the surface of the semi-insulating GaAs substrate 2 ishardly etched. Subsequently, the surface layer portion of thesemi-insulating GaAs substrate 2 is etched by changing the etchant againso as to form the groove bottom. Accordingly, the etching time of thesurface layer portion of the semi-insulating GaAs substrate 2 can beshortened so that the control of the depth of etching becomes accurate.As a result, the shortage of etching and the excessive etching hardlyoccur.

Accordingly, the isolation defect attributed to the shortage of etchinghardly occurs. Further, the excessive etching does not occur and hence,the large step is not generated. Since the large step is not generated,it is possible to prevent the disconnection of line at the steppedportion and the residue of metal when the line is formed at the steppedportion is eliminated whereby the short circuit between the lines can beprevented. Accordingly, the manufacturing yield factor of thesemiconductor device is enhanced and the product cost can be reduced.

(Embodiment 2)

FIG. 13 to FIG. 16 are drawings showing a method for manufacturing ahigh frequency power amplifier which incorporates a bias circuit thereinaccording to another embodiment of the present invention (embodiment 2).This embodiment 2 is characterized in that an emitter electrode and aSchottky electrode of a HBT are simultaneously formed using a samematerial.

FIG. 13 is a cross-sectional view of a portion of a semiconductorsubstrate on which an insulation film 14 which covers the collectorelectrode 12 and an ohmic electrode 42 for diode is formed. The drawingshows a stage in which the separation groove 13 shown in FIG. 8 in theembodiment 1 is formed and, thereafter, as shown in FIG. 9, aninsulation film 14 is formed. In this state, however, the Schottkyelectrode 41 is not formed. Also in this embodiment 2, an emitter layer9 a is formed using a photo resist as a mask and hence, there is nopossibility that the emitter electrode is used as the mask as in thecase of the embodiment 1. Accordingly, an emitter electrode is notformed even at this stage.

Then, contact holes are formed by selectively removing the insulationfilm 14 over the emitter layer 9 a and an n-type GaAs layer 6 in aSchottky diode forming region and electrodes are formed in these contacthole portions. As a result, an emitter electrode 11 is formed over theemitter layer 9 a and a Schottky electrode 41 is formed over the n-typeGaAs layer 6 in the Schottky diode forming region. The emitter electrode11 and the Schottky electrode 41 are simultaneously formed using a samematerial.

That is, after forming a WSi film having a thickness of 300 nm, forexample, by a sputtering method, dry etching is applied to the WSi filmusing a SF₆ gas or the like so as to form the emitter electrode 11 andthe Schottky electrode 41 shown in FIG. 14. This formation process issimilar to the process for forming the Schottky electrode 41 and theresistance film 46 in the embodiment 1 although they differ in material.

Then, as shown in FIG. 15, an insulation film 48 having a thickness of100 nm is formed over a whole area of a main surface of a wafer 25 and,thereafter, a resistance film 46 is selectively formed over aninsulation film 48 in a resistance element forming region. In thisembodiment 2, the resistance film 46 is formed of a NiCr film having athickness of 150 nm.

Then, as shown in FIG. 16, an interlayer insulation film 15 having athickness of 500 nm is formed over the whole area of the surface of thewafer 25 and, thereafter, contact holes are selectively formed and lines16 are selectively formed using a photolithography technique and anetching technique which are usually employed. As shown in FIG. 16, thecontact holes are formed such that the contact holes face the emitterelectrode 11, the base electrode 10, the collector electrode 12, theohmic electrode 42 for diode, the Schottky electrode 41 and two portionsof the resistance film 46. The lines 16 which are filled in thesecontact holes are electrically connected to respective electrodes(resistance films).

Although not shown in the drawings, another second lines may be formedapart from the lines 16 when necessary.

Subsequently, the insulation film 17 having a total thickness of 600 nmwhich is formed of the SiN film and the SiO₂ film is formed over thewhole area of the surface of the wafer 25 as a passivation film. Then,the thickness of the semi-insulating GaAs substrate 2 is reduced to 100to 50 μm, and the semi-insulating GaAs substrate 2 is divided by cuttinglongitudinally as well as laterally so as to produce the semiconductordevices.

In this embodiment 2, the emitter electrode 11 and the Schottkyelectrode 41 of the Schottky diode can be simultaneously formed usingthe same material (WSiN) so that the number of steps can be reducedwhereby the manufacturing cost of the semiconductor device can bereduced.

Further, in the same manner as the embodiment 1, it is possible toachieve the shortening of the base-collector junction length and thereduction of resistance of the collector layer. It is also possible toprevent the shortage of etching and the excessive etching in theformation of the separation groove.

(Embodiment 3)

FIG. 17 to FIG. 22 are drawings showing a method for manufacturing ahigh frequency power amplifier which incorporates a bias circuit thereinaccording to another embodiment of the present invention (embodiment 3).This embodiment 3 is an example of the method for manufacturingsemiconductors in which an emitter electrode, a Schottky electrode and aresistance film are simultaneously formed using a same material.

According to this embodiment 3, in the same manner as the embodiment 1,by sequentially laminating an n-type InGaP layer 3, an n-type GaAs layer4, an n-type InGaP layer 5, an n-type GaAs layer 6, a p-type GaAs layer7, an n-type InGaP layer 8, and an n-type GaAs layer 9 to a main surfaceof the semi-insulating GaAs substrate 2 using a MOCVD method or thelike, a wafer 25 is formed. Thereafter, using a photolithographytechnique and an etching technique which are usually employed, then-type GaAs layer 9 is selectively removed so as to form a mesa-shapedemitter layer 9 a from the n-type GaAs layer 9 as shown in FIG. 17.

Subsequently, as shown in FIG. 18, using a lift-off method in the samemanner as the embodiment 1, a base electrode 10 is formed over then-type InGaP layer 8 in the HBT forming region. The base electrode 10 issubjected to the alloying treatment and the base electrode 10 iselectrically connected to the p-type GaAs layer 7 which eventuallyconstitutes a base layer 7 a. Thereafter, the n-type GaAs layer (n-typeInGaAs/n-type GaAs layer) 9 is etched using a photo resist not shown inthe drawings and the base electrode 10 as an etching mask, and themesa-shaped layer 7 a whose periphery is positioned inside from aperiphery of the base electrode 10 is formed by side etching.

Then, as shown in FIG. 19, an insulation film 27 having a thickness of100 nm and made of SiO₂ is formed over a surface of the wafer 25 in thesame manner as the embodiment 1. Thereafter, contact holes for formingelectrodes are formed by selectively etching the n-type GaAs layer 6using a photolithography technique and an etching technique which areusually employed. Thereafter, using a lift-off method, a collectorelectrode 12 and an ohmic electrode 42 for diode are formed. Thecollector electrode 12 and the ohmic electrode 42 for diode are formedby a sputtering method using AuGe as a material until they obtain athickness of 300 nm.

In etching the above-mentioned n-type GaAs layer 6, wet etching whichuses a mixed aqueous solution of phosphoric acid and hydrogen peroxideis adopted and hence, although it is possible to completely etch then-type GaAs layer 6 in the etching region, the n-type InGaP layer 5below the n-type GaAs layer 6 is not etched. Accordingly, the thicknessof the n-type GaAs layer 4 is not changed so that collector resistancevalue is not changed whereby there is no possibility that the collectorresistance is increased by etching.

Subsequently, as shown in FIG. 20, in the same manner as the embodiment1, using a photolithography technique and an etching technique which areusually employed, the separation groove 13 for isolation is formed so asto make the HBT forming region and the Schottky diode forming regionelectrically independent from each other. Further, an insulation film 14made of SiO₂ is formed over the whole area of a main surface of thewafer 25.

Then, as shown in FIG. 21, using a technique similar to the techniqueused in the embodiment 1, the insulation film 14 formed over the emitterlayer 9 a and the n-type GaAs layer 6 in the Schottky diode formingregion are selectively removed thus forming the contact holes and,thereafter, the emitter electrodes 11, the Schottky electrode 41 and theresistance film 46 are simultaneously formed using the same material.

Subsequently, as shown in FIG. 22, in the same manner as the embodiment1, the interlayer insulation film 15 is formed over the entire area ofthe surface of the wafer 25 and, thereafter, contact holes areselectively formed and the lines 16 are selectively formed using aphotolithography technique and an etching technique which are usuallyemployed. As shown in FIG. 22, the contact holes are formed such thatthe contact holes face the emitter electrode 11, the base electrode 10,the collector electrode 12, the ohmic electrode 42 for diode, theSchottky electrode 41 and two portions of the resistance film 46. Thelines 16 which are filled in these contact holes are electricallyconnected to respective electrodes (resistance films).

To reduce the electric resistance of the emitter electrode 11 and theSchottky electrode 41, the film thickness of the WSiN film is madesmall, that is, 0.2 μm and, at the same time, the line 16 which isconnected to the WSIN film is overlapped to the WSiN film by a givenlength. Here, a gold layer may be used as the line 16 to reduce theelectric resistance.

Then, an insulation film 17 is formed over the whole area of the surfaceof the wafer 25 as a passivation film and the semi-insulating GaAssubstrate 2 is divided longitudinally and laterally by cutting so as tomanufacture semiconductor devices.

In this embodiment 3, the emitter electrode 11 of the HBT, the Schottkyelectrode 41 of the Schottky diode and the resistance film 46 of theresistance element can be simultaneously formed using the same material(WsiN having a thickness of 200 nm, for example) so that the number ofsteps can be reduced whereby the manufacturing cost of the semiconductordevice can be reduced.

Further, also in this embodiment 3, it is possible to achieve theshortening of the base-collector junction length and the reduction ofresistance of the collector layer as well as to prevent the shortage ofetching and the excessive etching in the formation of the separationgroove.

Although the inventions which are made by the inventors have beenspecifically explained in conjunction with the embodiments, it isneedless to say that the present inventions are not limited to theabove-mentioned embodiments and various modifications can be madewithout departing from the gist of the inventions.

To briefly recapitulate advantageous effects obtained by typicalinventions among the inventions disclosed in the present application,they are as follows.

(1) In forming the separation groove for isolation by etching, theshortage of etching and the excessive etching are hardly occur andhence, the manufacturing yield factor of the semiconductor device can beenhanced whereby the product cost can be reduced.

(2) Since the reduction of the base-collector capacitance can beobtained, it is possible to manufacture the semiconductor devices havinghetero junction bipolar transistors which exhibit the faster operationand the excellent high frequency characteristics.

1-41. (canceled)
 42. A method for manufacturing a semiconductor devicehaving a hetero-junction bipolar transistor (HBT), comprising the stepsof: (a) preparing a substrate having a first semiconductor layer of afirst type over the substrate, a second semiconductor layer of asecond-type over the first semiconductor layer, an InGaP layer of thefirst-type over the second semiconductor layer and a third semiconductorlayer of the first-type over the InGaP layer, the first type beingopposite to the second type; (b) forming an emitter electrode of the HBTover the third semiconductor layer; (c) after the step (b), forming thethird semiconductor layer into a mesa-shaped emitter layer of the HBT;(d) after the step (c), forming a base electrode over the secondsemiconductor layer outside the mesa-shaped emitter layer; (e) after thestep (d), forming an insulation film over the emitter and baseelectrodes; and (f) after the step (e), etching the second semiconductorlayer and InGap layer to form a mesa-shaped base layer of thehetero-junction bipolar transistor; (g) forming a collector electrodeover the first semiconductor layer.
 43. A method according to claim 42,wherein each of the first, second and third semiconductor layerscontains a GaAs layer.
 44. A method according to claim 42, wherein thefirst and second types are n-type and p-type, respectively.
 45. A methodaccording to claim 42, wherein in the step (f) the insulation film actsas an etching mask.